1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit having MIS (Metal-Insulator-Semiconductor) devices, and more particularly to a method of forming a channel stopper layer for the fabrication of a highly radiation-resistant semiconductor integrated circuit.
2. Description of the Prior Art
For isolating MIS devices such as MOS (Metal-Oxide-Semiconductor) transistors from each other on a substrate in a process of fabricating silicon semiconductor integrated circuits, it has generally been customary to form a thick field oxide film in a device separating region according to a LOCOS (Local Oxidation of Silicon) process. In manufacturing integrated circuits including n-channel MOS transistors, for reliable device isolation, a channel stopper layer may be formed by ion-implantation or diffusion of a p-type impurity, which is of the same conductivity type as a semiconductor substrate, underneath a field oxide film.
In integrated circuits for use in radiation environments such as outer space, a leakage current flowing between devices or the source and drain of an n-channel MOS transistor increases due to an accumulation of fixed charges caused in a field oxide film or due to an increase in the interfacial level at an interface between a field oxide film and a silicon substrate by the application of a radiation. Therefore, those integrated circuits for use in radiation environments are required to incorporate a channel stopper layer underneath the field oxide film in order to suppress the leakage current.
FIGS. 1, 2, and 3 are illustrative of a conventional process of manufacturing a semiconductor device having a channel stopper layer.
First, as shown in FIG. 1, a field oxide film 202 for device isolation is formed in a p-type silicon semiconductor substrate 201 by a LOCOS process, and a resist film 203 is coated on the entire surface of the semiconductor substrate 201 including the field oxide film 202. Then, a window 204 is defined in the resist film 203 by photolithography. As well known in the art, the field oxide film 202 includes a central thicker portion and a peripheral thin region known as a bird's beak. The window 204 is positioned over the central thicker portion of the field oxide film 202, so that the surface of the central thicker portion of the field oxide film 202 is exposed at the bottom of the window 204. Using the resist film 203 as a mask, ions of boron (B.sup.+) are introduced through the window 204 by way of ion implantation at a dosage of 10.sup.14 /cm.sup.2 with an acceleration energy ranging from 100 to 180 keV, for example. Thereafter, the assembly is annealed at 800.degree. C. for 30 minutes, for example, thereby to activate the introduced boron. As a result, as shown in FIG. 2, a channel stopper layer 205 which contacts with the field oxide film 202 is formed in the p-type semiconductor substrate 201 at a region underneath the central portion of the field oxide film 202.
Since the boron ions are applied to only the central portion of the field oxide film 202, a region 209 free of any channel stopper layer is created underneath the peripheral thin region or the bird's beak of the field oxide film 202. FIG. 3 is a plan view of the assembly shown in FIG. 2, which is a cross-sectional view taken along line II--II' of FIG. 3. If n-channel MOS transistors formed on the p-type semiconductor substrate 201 are isolated from each other by the field oxide film 202, then when radiation is applied to an integrated circuit of the above cross-sectional structure, a leakage current flowing between devices or the source and drain of a MOS transistor through the region 209 free of any channel stopper layer increases due to an accumulation of fixed charges caused in the field oxide film 202 or due to an increase in the interfacial level at an interface between the field oxide film 202 and the silicon substrate 201.
In the example shown in FIGS. 1 through 3, the ions of boron are applied to only the central portion of the field oxide film 202. However, it is possible to apply ions of boron to the entire area of a field oxide film by way of ion implantation.
FIGS. 4 through 6 illustrate a conventional process of manufacturing a semiconductor integrated circuit by applying ions of boron to the entire area of a field oxide film by way of ion implantation.
First, as shown in FIG. 4, a field oxide film 302 is formed in a p-type silicon semiconductor substrate 301 by a LOCOS process, and a resist film 303 is coated on the entire surface of the semiconductor substrate 301. Then, a window 304 is defined in the resist film 303 by photolithography such that the entire surface of the field oxide film 302 is exposed through the window 304. Ions of boron (B.sup.+) are introduced through the window 304 by way of ion implantation at a dosage of 10.sup.14 /cm.sup.2 or lower with an acceleration energy ranging from 100 to 180 keV, for example. Thereafter, the assembly is annealed to activate the introduced boron. As a result, as shown in FIG. 5, a channel stopper layer 305 is formed in the semiconductor substrate 301.
Inasmuch as the boron ions are applied to substantially the entire area of the field oxide film 302 under a high energy condition in the range from 100 to 180 keV, boron ions are introduced deeply into the p-type silicon substrate 301 at the area of immediately below the thin film or bird's beak in the periphery of the field oxide film 302, creating a region 309 on the lower surface of the periphery of the field oxide film 302 out of contact with the channel stopper layer 305. FIG. 6 is a plan view of the assembly shown in FIG. 5, which is a cross-sectional view taken along line V--V' of FIG. 6. When radiation is applied to an integrated circuit of the above cross-sectional structure, a leakage current flowing between devices or the source and drain of a MOS transistor through the region 309 on the lower surface of the field oxide film 302 out of contact with the channel stopper layer 305 increases due to an accumulation of fixed charges caused in the field oxide film 302 or due to an increase in the interfacial level at an interface between the field oxide film 302 and the silicon substrate 301.
According to a process disclosed in Japanese laid-open patent publication No. Sho-61-226967 (JP, A, 61-226967), before a field oxide film is formed, ions are applied at two stages to an area where the field oxide film will be formed, by way of ion implantation, forming a higher-density impurity region and a lower-density impurity region, and thereafter a field oxide film is formed thereby to provide a higher-density channel stopper layer and low-density channel stopper layer beneath the filed oxide film for thereby reducing any leakage current of an n-channel MOS transistor and minimizing any parasitic capacitance. The same level of ion acceleration energy (40 kev) is used for the higher-density impurity region and the lower-density impurity region. The disclosed process makes it possible to reduce the concentration of an impurity in the channel stopper layer at a boundary near a device forming region. However, the disclosed process is problematic in that it fails to assemble devices in a highly integrated fashion because the impurity is diffused laterally from the channel stopper layer in a subsequent step of forming a field oxide film.
Japanese laid-open patent publication No. Hei-5-555204 (JP, A, 5-55204) discloses a technique of suppressing the diffusion of an impurity from a channel stopper layer into a device forming region and preventing a junction breakdown voltage from being lowered, by etching back a field oxide film to a position corresponding to a substrate surface and thereafter forming the channel stopper layer by way of ion implantation. According to such a structure, however, the lower surface of the field oxide film and the channel stopper layer are not held in contact with each other at the bird's beak of-the field oxide film, so that a leakage current will be increased upon exposure to radiation, as with the arrangement described above with reference to FIGS. 4 through 6.
According to the conventional process of manufacturing a semiconductor integrated circuit by forming a channel stopper layer by way of the ion implantation or diffusion of an impurity prior to the formation of a field oxide film, since the impurity is laterally diffused when the field oxide film is formed, it is necessary to increase the distances between devices on the substrate, resulting in an increased integrated circuit chip area.
According to the process of introducing an impurity by way of ion implantation after a field oxide film is formed, it is necessary to increase ion acceleration energy because the ions have to be introduced through the field oxide film. If the ion acceleration energy is increased, then it tends to damage the crystal of the semiconductor substrate. Therefore, it has been customary to effect only one cycle of ion implantation. Accordingly, the lower surface of the periphery of the field oxide film is held out of contact with the channel stopper layer. When an integrated circuit thus manufactured is exposed to radiation, there is developed a region where an interfacial level is created at the interface between the field oxide film and the semiconductor substrate, with the result that a leakage current flowing between devices or the source and drain of an n-channel MOS transistor increases.